1. Technical Field
The present invention relates to a configuration of an integrated circuit for recovering data that is asynchronous, where a clock is not sent with the data.
2. Related Art
In a synchronous environment, a clock is forwarded along with the data. The clock is frequency locked to the data. Resources of a number of types of integrated circuits (ICs), such as an FPGA, can be used to recover the data using the accompanying clock signal.
In asynchronous environments, however, no forwarding clock is provided. Data recovery circuitry in an IC may use a self-generated system clock to try and match the incoming data rate, but since the two rates are generated from two different clock sources, a nominal difference is created between the two rates. The incoming data will typically exhibit a certain amount of frequency wander (i.e. 200 ppm) from the system clock of the IC. Sampling the incoming data with the system clock with no intervening mechanisms will result in bit errors. Traditionally two methods used to recover data in an asynchronous environment as described below.
In a first data recovery method, multiple phases are generated from the system clock to over sample the incoming data. In FPGAs such as the Virtex-4 made by Xilinx, Inc. of San Jose, Calif., the Digital Clock Manager (DCM) is typically used to generate multiple phases of the system clock to over sample the data. Then, using a system of edge detection mechanisms, a state machine picks the correct sample to forward to the rest of the system. The disadvantage of this method is that every phase of the over sampling clock generated must be routed through a global clock buffer, severely limiting the number of global clock buffers available for general use. Furthermore, the use of multiple global clock buffers dramatically increases the power consumption of the system.
In a second recovery method, a phase locked loop (PLL) is used to synthesize a frequency matched clock from the incoming data. The disadvantage of this scheme is the necessity for additional components, namely the PLL and loop filters.